The idea
Etch is a local hardware-design cockpit that turns a natural-language requirement into a typed design spec, candidate RTL, independent verification artifacts, EDA gate results, correctness-first ranking, physical readiness records, and a proof dossier.
The problem
AI can generate RTL, but generation alone does not prove a chip design should be trusted. Hardware workflows need durable evidence: what passed, what failed, which tools were missing, and which claims are still out of bounds.
How it works
I built a FastAPI backend, React/Vite workbench, Electron shell, file-backed run workspace, deterministic FIFO demo, optional LLM proposal path, simulation/formal/synthesis adapters, claims ledger, and status-aware cockpit views for trust and diagnostics.
System
Verification-first hardware path
Natural-language intent becomes typed specs, ranked candidates, and a proof dossier with explicit missing-tool states.
The completed example is a synchronous FIFO. Larger hardware designs belong to the roadmap; each would need its own verification evidence.
The work
The saved FIFO dossier records simulation, bounded-formal checks, and synthesis results. Missing tools and pending physical signoff remain visible alongside the completed checks.
Saved FIFO example · simulation · bounded-formal checks · synthesis
Where it stands
The saved vertical slice carries a synchronous FIFO through typed specs, three candidates, independent oracle artifacts, simulation and bounded-formal gates, Yosys 0.66 metrics, explicit missing-tool states, and Markdown/JSON proof dossiers. Physical signoff remains pending.
Physical signoff pending
Simulation and bounded-formal results apply to the saved example and its checked bounds. They do not establish foundry signoff or a fabricated chip.