Verification-First Hardware Design
ETCH
Verification-first hardware design from intent to evidence.
A proven
50-cycle sim
BMC depth 32
Yosys 0.66
Physical signoff pending
Problem
AI can generate RTL, but generation alone does not prove a chip design should be trusted. Hardware workflows need durable evidence: what passed, what failed, which tools were missing, and which claims are still out of bounds.
System
FIFO to arbiter to AXI-lite to DMA to cache to RV32I to accelerator to SoC ladder with verification gates.
Evidence
Saved FIFO run dossier, Yosys 0.66 synth metrics, sim and bounded-formal pass records, and verification-gate sequence as the architecture story.
Outcome
The saved vertical slice carries a synchronous FIFO through typed specs, three candidates, independent oracle artifacts, simulation and bounded-formal gates, Yosys 0.66 metrics, explicit missing-tool states, and Markdown/JSON proof dossiers. Physical signoff remains pending.
System
Verification-first hardware path
Natural-language intent becomes typed specs, ranked candidates, and a proof dossier with explicit missing-tool states.
Approach
I built a FastAPI backend, React/Vite workbench, Electron shell, file-backed run workspace, deterministic FIFO demo, optional LLM proposal path, simulation/formal/synthesis adapters, claims ledger, and status-aware cockpit views for trust and diagnostics.
Constraints
Hardware proof is staged; claims track the verified ladder, not aspirational silicon.
Evidence
Inside the system
