05 /
ETCH
Verification-First Hardware Design
From natural-language intent to RTL evidence, gates, and proof dossiers.
- Role
- Founder & Engineer
- Status
- Public repository · local vertical slice
- Verified proof
- Saved FIFO run · simulation pass · bounded-formal pass · signoff pending
Physical signoff pending
From constraint to evidence
The work, end to end.
Problem
AI can generate RTL, but generation alone does not prove a chip design should be trusted. Hardware workflows need durable evidence: what passed, what failed, which tools were missing, and which claims are still out of bounds.
Approach
I built a FastAPI backend, React/Vite workbench, Electron shell, file-backed run workspace, deterministic FIFO demo, optional LLM proposal path, simulation/formal/synthesis adapters, claims ledger, and status-aware cockpit views for trust and diagnostics.
Outcome
The saved vertical slice carries a synchronous FIFO through typed specs, three candidates, independent oracle artifacts, simulation and bounded-formal gates, Yosys metrics, explicit missing-tool states, and Markdown/JSON proof dossiers. Physical signoff remains pending.
Overview
What shipped
Etch is a local hardware-design cockpit that turns a natural-language requirement into a typed design spec, candidate RTL, independent verification artifacts, EDA gate results, correctness-first ranking, physical readiness records, and a proof dossier.
Built with
- Python
- FastAPI
- React
- Electron
- Yosys
- Verilator
Evidence
Inside the system
